The current trend in chip integration, such as for system-on-a-chip (SOC) applications, is to include all of the blocks (e.g., processor, memory, phase-locked loops (PLL's), input/output blocks, etc.) in a single chip. However, with the increasing complexity of the blocks being integrated, it is becoming more difficult to integrate all of the blocks into a single chip, and to perform testing and verification. In addition, as the blocks in these chips become larger and more complex, the number of signal lines and interconnection structures (e.g., bond wires) is increasing, which can cause a routing congestion problem. The interconnection structures are also becoming longer and operate at higher speeds, which increases power consumption.
The processors in SOC applications are becoming faster and faster. However, not all of the blocks in SOC chips are high performance blocks like the processor. By increasing the speed of the processor, there is typically a cost penalty for the entire integrated chip because not all of the blocks need that same performance. The cost is increased because all of the blocks in the chip are typically optimized around the speed and performance requirements of the processor.
Multi-chip (i.e., multi-die) packages have been developed that include multiple semiconductor die in a single package. However, conventional multi-chip packages typically include a large number of signal lines between the chips, and these packages typically suffer from the same routing congestion and other problems described above with respect to single-chip packages.